1. Field of the Invention
This invention relates to multi-clock domain digital data communication and, more particularly, to detecting the alignment of multiple clock signals.
2. Description of the Related Art
New techniques to ensure the reliability of the communication of digital data have become necessary as the speed of communication links has increased. Particularly within computer memory systems, a reference clock may accompany parallel digital data so as to provide a mechanism for determining the appropriate time to sample the data. However, it is often the case that multiple clock domains are established within a given communications system due to the difficulties involved in distributing a single clock throughout a large system. Although the clocks of each individual clock domain may or may not have the same frequency, it is to be expected that the phase relationship between any two clocks in different domains will vary depending on changes in voltages and temperature between the domains over time. Jitter in the phase offset between a transmitting clock and a receiving clock tends to move the sampling point away from the ideal point in the received data signal, resulting in poor timing margins and/or a higher bit-error-rate (BER). The higher the speed at which a communications link is clocked, the more significant the effects of phase jitter become. In addition, if the ratio of the clock frequencies across a given boundary is not an integral multiple, determining when the respective clocks are aligned can be difficult. Therefore, it is desirable to have a mechanism to determine when to sample the data across a clock boundary while maintaining a robust timing margin thereby reducing the impact of phase changes between clock domains and enabling higher communication speeds.
It can be important to pick a point in time “deterministically” when one or more ratio'ed synchronous clocks are aligned, especially when it pertains to domain crossing between such clocks. “Ratio'ed synchronous” clocks have frequencies that are rational multiples of a single reference clock. This can happen when a single clock reference input to a chip is multiplied internally by one or more PLLs.